This invention is in the field of solid-state integrated circuit measurement. Embodiments of this invention are directed to measurement of capacitor mismatch in integrated circuits, and more particularly to the measurement of capacitor mismatch between capacitors of different construction from one another.
As is fundamental in the art, the controlled and successful manufacture of integrated circuits requires measurement of various parameters and behavior in the manufactured devices. In many modern integrated circuits, one particularly important parameter is capacitance, including both the capacitance of structures that are intended to be capacitors in the circuit function itself, and also the parasitic capacitance exhibited by conductors, transistors (e.g., junction capacitance, gate capacitance), and other circuit features. Manufacturing variations, temperature dependence, voltage dependence, and other variations in manufacturing parameters and operating conditions cause variations in the capacitance exhibited by a given structure over a population of manufactured integrated circuits, and also variations in capacitance among capacitors within a given integrated circuit.
Some modern integrated circuits are particularly sensitive to capacitor mismatch within their circuit functions. For example, modern analog-to-digital converters (ADCs) are particularly sensitive to capacitor mismatch and variations in capacitance. As known in the art, switched-capacitor ADCs rely on one or more weighted capacitor arrays to provide a digital estimate of a sampled input analog signal; mismatches among capacitors within an array result in variations from the binary-weighting or other weighting scheme, and non-linearities in the digital output. Differential switched-capacitor ADCs and double-sampling switched-capacitor ADCs are also subject to mismatch between capacitors in different arrays, giving rise to conversion errors. Other types of ADCs, such as pipelined ADCs, as well as other analog and digital integrated circuit functions, are also vulnerable to capacitor mismatch.
In addition to capacitor mismatch due to manufacturing variations, capacitor mismatch is necessarily present between capacitors of different structure. For example, the array capacitors in many modern ADCs are constructed as metal-to-metal capacitors, with parallel plates formed in first and second metal layers in the integrated circuit. Other capacitors in the same circuit may be formed with a polysilicon plate overlying a parallel plate in an active region in the underlying substrate or well region. Parasitic capacitances of switching transistors in the ADCs are essentially poly-to-active capacitors. The behavior of the poly-to-substrate capacitor with voltage is substantially different from that of a metal-to-metal capacitor, considering the effect on stored charge by changes in the depletion region in substrate, over variations in voltage.
Capacitance variations and capacitor mismatch have been addressed in the design of modern ADCs. Examples of calibration and correction techniques are described in U.S. Pat. Nos. 7,136,006 and 6,891,486, both commonly assigned herewith, and in Tan et al., “Error Correction Techniques for High-Performance Differential A/D Converters”, J. Solid-State Circ., Vol. 25, No. 6 (IEEE, 1990), pp. 1318-27, all of which are incorporated herein by reference.
For purposes of calibration, trimming, and process control, it is of course useful to measure capacitor behavior in manufactured devices, for example in wafer form along with functional and parametric electrical test. A conventional circuit for measuring mismatch between capacitors is shown in FIG. 1. Capacitors C1, C2 are the capacitors to be compared with one another in this circuit, and are connected in series between terminals V1, V2. In practice, capacitor C2 may be a “reference” capacitor, against which the capacitance of capacitor C1 is to be measured. Node VINT between capacitors C1, C2 is connected to the gate of p-channel metal-oxide-semiconductor (MOS) transistor 4, the drain of which is at ground and the source of which is connected through current source 2 to bias voltage Vdd. The body of transistor 4 is connected to its source, in this example.
In operation, current source 2 is biased to produce a constant current I1, and bias voltage Vdd is sufficiently positive (relative to the ground voltage at the drain of transistor 4) to place transistor 4 in saturation. As well-known in the art, transistor 4 operates as a “source follower” under those conditions; because transistor 4 is in saturation, the constant source-drain current I1 forces its gate-to-source voltage Vgs to be constant. As such, output voltage VOUT at the source of transistor 4 follows changes in the voltage at its gate, which is at node VINT.
To perform measurement of the relative capacitances of capacitors C1, C2 in this conventional arrangement, the voltage at node V2 is held constant (e.g., at ground) and the voltage at node V1 is ramped over time. The voltage at intermediate node VINT will respond to the ramped voltage V1 by also ramping, but at a flatter slope according to the voltage divider of capacitors C1, C2:
      VINT    ⁡          (      t      )        =      V    ⁢                  ⁢    1    ⁢                  (        t        )            ·              (                              C            ⁢                                                  ⁢            1                                              C              ⁢                                                          ⁢              1                        +                          C              ⁢                                                          ⁢              2                                      )            Ideally, the output voltage VOUT from the source follower of transistor 4 increases with the ramping voltage VINT(t) at the same slope S:
  S  =            C      ⁢                          ⁢      1                      C        ⁢                                  ⁢        1            +              C        ⁢                                  ⁢        2            By determining the slope of VOUT(t) in response to the ramped voltage at node V1, one can then determine the relative capacitances of capacitors C1, C2:
            C      ⁢                          ⁢      2              C      ⁢                          ⁢      1        =      S          (              1        -        S            )      
In practice, however, the behavior of the source follower circuit of FIG. 1 is not ideal, especially in modern sub-micron transistors. In the circuit of FIG. 1, the drain-to-source voltage of transistor 4 changes as the voltage at node VINT increases. This modulation of the drain-to-source voltage causes some of the changes in the gate voltage to be consumed in charging or discharging parasitic junction capacitances in the device. Furthermore, due to the mechanism of drain-induced barrier lowering, transistor threshold voltages modulate in response to changes in drain-to-body node voltage. These effects cause the slope of output voltage VOUT(t) to not purely reflect the relative capacitances of capacitors C1, C2, but will also reflect capacitive effects and also variations in the threshold voltage of transistor 4 over the duration of the measurement. The resulting output voltage VOUT(t) will thus include non-linearities, which can be substantial. For example, threshold voltage modulation of on the order of 10 mV has been observed, in connection with this invention, for an example of transistor 4 with a nominal threshold voltage of about 0.35 volts. The resulting inaccuracy in capacitance measurement is incompatible with capacitors such as those intended for precision circuits such as high-performance ADCs.